1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more particularly, to a construction of a data output section of a clock synchronous type semiconductor memory that is operated synchronized with a clock signal externally applied. More specifically, the present invention relates to a construction that is capable of transmitting internal data at high speed in a clock synchronous type semiconductor memory.
2. Description of the Background Art
FIG. 37 is a diagram schematically showing a portion related to a data reading in a conventional clock synchronous type semiconductor memory device. In FIG. 37, the data reading section includes: an internal clock generation circuit 1 for buffering an external clock signal CLKe to generate an internal clock signal CLKi, a clock control circuit 2 for generating various control clock signals such as CLKR and CLKO in accordance with internal clock signal CLKi and an operation mode instruction (command) from an address/command control circuit 3, address/command control circuit 3 for receiving an address and a command ACG and for generating an internal address and an operation mode instruction signal, a memory circuit 4 for reading stored data from a memory cell under a control of address/command control circuit 3, a reading circuit 5 for transferring data read from a selected memory cell of memory circuit 4 in accordance with read out clock signal CLKR from clock control circuit 2, and an output control circuit 6 for transferring data transferred from reading circuit 5 in accordance with output clock signal CLKO from clock control circuit 2 to generate an external read data Q.
In accordance with the address and command ACG, address/command control circuit 3 applies a command for specifying a data reading instruction to clock control circuit 2 in reading data. Address/command control circuit 3 also applies a reading instruction signal for instructing a data reading operation to memory circuit 4 together with an address signal.
Memory circuit 4 includes memory cells that are arranged in rows and columns, and a memory cell selection circuit for selecting a row and column of the memory cells in accordance with the internal address signal from address/command control circuit 3. Reading circuit 5, the construction of which will be described later, includes a preamplifier and a shifter, amplifies data of the selected memory cell of memory circuit 4, and transfers the resultant signal in accordance with reading clock signal CLKR.
Output control circuit 6, the construction of which will be described later, takes in data transferred from reading circuit 5 in accordance with output clock signal CLKO, executes a buffering process on the data for external output. Both of these reading clock signal CLKR and output clock signal CLKO are generated by using a delay circuit, etc., based upon internal clock signal CLKi.
In the synchronous type semiconductor memory device shown in FIG. 37, an address/command capturing is carried out in synchronization with a rising or falling edge of internal clock signal CLKi generated by buffering external clock signal CLKe, and internal read out data is transferred in accordance with reading clock signal CLKR. Then, output control circuit 6 buffers the internal read out data in synchronization with a rising or falling edge of output clock signal CLKO to generate external data Q. When this semiconductor memory device is operated in a signal data rate mode, the external data outputting is carried out in response to one of rising and falling edges of internal clock CLKi. In contrast, when this semiconductor memory device is operated in a double data rate mode, the data outputting is carried out in response to both of the rising and falling edges of internal clock CLKi.
FIG. 38 is a diagram schematically showing the construction of reading circuit 5 shown in FIG. 37. In reading circuit 5, data of a plurality of bits that is read out in parallel with each other from memory circuit 4 is selectively transferred to an internal read data line 10. FIG. 38 schematically shows the construction related to one-bit data.
In FIG. 38, reading circuit 5 includes a preamplifier 5a that amplifies data read out on a pair of internal data lines IO and ZIO from memory circuit 4 in response to the activation of a preamplifier activation signal PAEj, and a shifter 5b that transfers the amplified data of preamplifier 5a in synchronization with shift clock signal CLKf. This shifter 5b includes an output driver for driving an internal read data transmission line 10. Preamplifiers 5a are placed in parallel with each other for internal read data transmission line 10 so that an output signal of the preamplifier activated by preamplifier activation signal PAEj is transmitted to internal read data transmission line 10 through the corresponding shifter.
Preamplifier activation signal PAEj is generated based upon a main preamplifier activation signal PAE and a preamplifier selection signal, and used for activating one of a plurality of preamplifiers placed in parallel with each other. Shifter 5b, which is a column latency shifter, carries out a transferring operation in a (column latencyxe2x80x942) cycle period, and adjusts the transfer period of the internal data so that, after a lapse of the column latency period since the receipt of a read command, valid data is externally outputted. A shift clock signal CLKf is generated based upon internal clock signal CLKi and the preamplifier selection signal so that the shift clock signal is applied to the shifter that is arranged in associated with the selected preamplifier.
A read data driver may be placed at an output section of this shifter 5b. Through internal read data transmission line 10, upon reading data, data Qi of one bit is transferred in accordance with internal clock signal CLKi. Preamplifier activation signal PAEj and a selection signal SELj are respectively generated based upon the column address signal, and the activation timings thereof are determined based upon internal clock signal CLKi.
FIG. 39 is a diagram schematically showing the construction of output control circuit 6 shown in FIG. 37. In FIG. 39, output control circuit 6 includes a read data detector 6a for taking in and amplifying internal reading data Qi on internal read data transmission line 10 in response to the activation of a detector enable signal DEN, and an output buffer circuit 6b for transferring the amplified data received from read data detector 6a to generate external output data Q, in accordance with an output clock signal CLKQ.
Read data detector 6a latches read out data Qi in synchronization with internal clock signal CLKi, and amplifies the latched data to apply the resultant data to output buffer circuit 6b. Output clock signal CLKO, shown in FIG. 37, corresponds to a pair of read data detector enable signal DEN and output signal CLKQ, and output clock signal CLKQ is generated by delaying internal clock signal CLKi by a predetermined period of time in reading data. In the same manner, detector enable signal DEN is also activated after a lapse of a predetermined time period based upon internal clock signal CLKi.
The delay times of these signals DEN and CLKQ are adjusted in accordance with the frequency of clock signal CLKi, and also changed in accordance with the frequency of clock signal CLKi.
Therefore, in this output control circuit 6 also, the data amplifying and transferring operations are carried out in synchronization with internal clock signal CLKi so that output data Q is outputted in synchronization with internal clock signal CLKi.
FIG. 40 is a timing chart representing the data reading operation of reading circuit 5 shown in FIG. 38. As shown in FIG. 40, upon receipt of the read command instructing a data reading operation, a read activation signal RP is activated for a predetermined period (during a burst length period) in synchronization with a rise of internal clock signal CLKi. Here, the burst length period indicates the number of pieces of data successively outputted through one data terminal when one read command is applied.
When read activation signal RP is activated, a main preamplifier activation signal MPAE is activated in accordance with internal clock signal CLKi. According to main preamplifier activation signal MPAE and a preamplifier selection signal, generated in accordance with the column address signal applied at the time of the application of the read command, preamplifier activation signal PAEj shown in FIG. 38 is activated. When main preamplifier activation signal MPAE (preamplifier activation signal PAEj) is activated, a preamplifier 5a, shown in FIG. 38, is activated so that data on internal read data lines IO and ZIO is amplified to generate the resultant, amplified data PD for application to shifter 5b. 
A shift clock signal CLKf is generated in accordance with internal clock signal CLKi so that, when shift clock signal CLKf goes high, shifter 5b takes in output data PD of preamplifier 5a, and when shift clock signal CLKf goes low, shifter 5b is set to the latch state. Therefore, in shifter 5b, the internal data changes in synchronization with a rise of this shift clock signal CLKf.
In accordance with shift clock CLKf, shifter 5b carries out a shifting operation for a predetermined clock cycle period so that internal read data Qi is transmitted to internal read data transmission line 10. Here, FIG. 40 shows one example in which shifter 5b carries out a shifting operation of one clock cycle for a case in which column latency corresponds to 3.
Shift clock signal CLKf is generated in accordance with internal clock signal CLKi and read activation signal RP independently of main preamplifier activation signal MPAE through a separated path from that of main preamplifier activation signal MPAE. This shift clock signal CLKf has a delay time td with respect to internal clock signal CLKi. This delay time td is constant when the frequency of clock signal CLKi is constant, and generated by using a delay circuit having a delay time thereof adjusted in accordance with the clock frequency.
Therefore, when, after main preamplifier activation signal MPAE is activated and output data PD of preamplifier 5a is set to the definite state, shift clock signal CLKf goes high, shifter 5b can accurately take in and transfer output data PD of amplifier 5a. 
FIG. 41 is a diagram schematically showing the relationship in phase between shift clock signal CLKf and main preamplifier activation signal MPAE. After the read command is applied, the data of a selected memory is transferred to a pair of internal data lines IOP (IO, ZIO). The time required for the data of selected memory cell to be transmitted, through internal line pair IOP to preamplifier 5a is determined in advance by an interconnection delay and such in the semiconductor memory device. With this delay time taken into consideration, main amplifier activation signal MPAE is activated after a lapse of time tA since the read command is applied. In accordance with activation of main preamplifier activation signal MPAE, output data PD of the preamplifier is allowed to change.
When the read command is applied, shift clock signal CLKf is generated in a path separated from that of main preamplifier activation signal MPAE, and rises after a lapse of time td in accordance with internal clock signal CLKi. Shift clock signal CLKf has a fixed pulse width. Therefore, in the case when this High level period of shift clock signal CLKf is completed prior to the change in output data PD of the preamplifier, an erroneous data reading is carried out, failing to carry out an accurate data reading operation.
This delay time td that shift clock signal CLKf has is optimally set in accordance with the frequency of clock signal CLKi at the time of designing, however, this delay time td tends to vary due to deviations in manufacturing parameters or others. Therefore, in the case when these main preamplifier activation signal MPAE and shift clock signal CLKf are formed through separated, individual paths, a timing margin needs to be taken into consideration, and a high speed operation can not implemented.
It is desirable for a data transmitting time from preamplifier 5a to shifter 5b to be made as short as possible from the viewpoint of a high speed access. Therefore, the activation timing of preamplifier 5a is normally changed in accordance with the operation frequency, and at the time of a high speed operation, preamplifier 5a is activated as fast as possible. At this time, shifter 5a is also made faster in activation timing correspondingly, and in order to advance the activation timing of shifter 5b, the activation timing of shifter 5b is changed in accordance with internal clock signal CLKi in the same manner. Therefore, the activation timing of each of preamplifier 5a and shifter 5b needs to be changed in accordance with the frequency of the clock signal, causing the above-mentioned problem with a timing margin or the like at the time of this change of activation.
Moreover, as shown in FIG. 40, preamplifier 5a latches output data PD for one clock cycle period. Therefore, in the case when preamplifier 5a latches output data PD for one clock cycle period, as indicated by a broken line in FIG. 41, if shift clock signal CLKf changes after the change of output data PD of the preamplifier, the set up time and hold time of the preamplifier output data with respect to shift clock signal CLKf need to be ensured. Consequently, there arises a problem that the cycle time could not shortened, and therefore, it is not possible to implement a high speed operation.
Thus, in reading circuit 5, in the case when shift clock signal CLKf for shifter 5b is generated with a predetermined delay time based upon internal clock signal CLKi in a path separated from that of preamplifier activation signal PAEj (main preamplifier activation signal MPAE) of preamplifier 5a, the timing margin needs to be set greater, and the set up/hold time of preamplifier output data PD with respect to shift clock signal CLKf needs to be ensured. Thus, there arises the problem that it is not possible to carry out a data reading operation at high speed.
It could be considered that shift clock signal CLKf is generated in response to the activation of preamplifier activation signal MPAE. In this case, however, an inherent delay time occurs from the activation of the preamplifier to the generation of the shift clock signal, causing an adverse effect on the high speed operation.
FIG. 42 is a diagram schematically showing the construction of a part for generating the signals transmitted to output control circuit 6 shown in FIG. 39. A control clock generation circuit shown in FIG. 42 is included in clock control circuit 2 shown in FIG. 37.
In FIG. 42, clock control circuit 2 includes a read control circuit 2a for generating read activation signal RP in accordance with read command READ, a detector clock generation circuit 2b for generating detector enable signal DEN by delaying internal clock signal CLKi by a predetermined time in accordance with the activation of read activation signal RP from read control circuit 2a, and an output clock generation circuit 2c for generating output clock signal CLKQ with a predetermined delay time in synchronization with internal clock signal CLKi upon activation of read activation signal RP. These detector enable signal DEN and output clock signal CLKQ each have a delay time that is set in accordance with the frequency of internal clock signal CLKi, and also have a predetermined time width.
As shown in FIG. 42, detector enable signal DEN and output clock signal CLKQ are generated in separated, individual paths. Upon data outputting, output clock signal CLKQ is generated during a burst length period in accordance with the activation of output enable signal OE generated inside thereof, in data outputting. The generation start timing of output clock signal CLKQ is determined in accordance with a column latency CL. Detector enable signal DEN needs to be activated at a faster timing as compared with output clock signal CLKQ, with the data latching and transferring operation in output buffer circuit 6b taken into account. Thus, data clock generation circuit 2b and output clock generation circuit 2c are formed of individual, separated circuits.
Therefore, as shown in FIG. 43, after a lapse of time tB since the read command is applied, internal read data Qi is transmitted to read data detector 6a as shown in FIG. 39, and set to the definite state. In the case where the delay time of detector enable signal DEN becomes shorter due to deviations of transistor parameters or other and detector enable signal DEN is activated at time t0, the read detector 6a takes in and amplifies internal read data Qi in the non-definite state and therefore, it becomes impossible to carry out an accurate data reading operation.
The read data detector 6a is set to the latching state when detector enable signal DEN is activated, and the latched data is amplified. Therefore, when read data detector 6a enters the latching state at time t0, detector enable signal DEN is activated before internal read data Qi is made definite, resulting in an inaccurate data reading operation. Consequently, it is necessary to activate detector enable signal DEN at time t1 after internal read data Qi is made definite, and it is therefore necessary to take into consideration a margin for the delay time of the detector enable signal. Thus, it becomes impossible to implement a high speed operation.
In particular, the time required for the data to be transmitted by reading circuit 5 shown in FIG. 38 from a selected memory cell to read data detector 6a through the internal read data transmission line is predetermined in accordance with the frequency of the clock signal by taking a margin in this reading circuit 5 into consideration. Therefore, in the case where the delay time of the detector enable signal DEN varies due to variations in process parameters or the like, it becomes impossible to implement an accurate data reading operation.
In particular, in the case when the time tB is changed in accordance with the frequency of the clock signal, it is necessary to also adjust the generation timing of detector enable signal DEN in response to the changing, and a high speed operation can not be implemented due to the above-mentioned problem with timing.
Since it is necessary to take this margin of detector enable signal DEN into consideration, it is necessary to allow output buffer circuit 6b to perform the data transfer operation, with output clock signal CLKQ being set to the activated state at time tc after detector enable signal DEN is activated at time t1, and it becomes impossible to implement a high speed data reading operation. Moreover, at this time, since output clock signal CLKQ and detector enable signal DEN are produced through separated individual paths, output clock signal CLKQ needs to be activated by taking the timing margins of these detector enable signal DEN and output clock signal CLKQ into consideration. Consequently, the activation timing of the output buffer circuit is further delayed, and it becomes impossible to implement a data outputting operation at high speed.
In the case of a clock synchronous type memory, output buffer circuit 6b is required to output data in synchronization with the edge of the clock signal. Therefore, when the output buffer circuit is operated in response to output clock signal CLKQ, output buffer circuit 6b needs to be operated by taking signal propagation delays in data detector 6a and the buffer circuit 6b into consideration. In this case, the control signals DEN and CLKQ for these circuits 6a and 6b are generated in accordance with clock signal CLKi, and this timing adjustment becomes difficult.
More specifically, assuming that the signal propagation delay in each of data detector 6a and output buffer 6b is 2 ns (nanosecond) and that the clock cycle is 10 ns, detector enable signal DEN is activated after a lapse of 8 ns relative to the edge of clock signal CLKi. When this clock cycle becomes 8 ns, for example, it is necessary to activate detector enable signal DEN after a lapse of 6 ns relative to the edge of the clock signal. Therefore, it is necessary to change the activation timings of these activation control signals DEN and CLKi for these output circuits in accordance with the cycle time of the clock signal, or the frequency thereof, and it is therefore necessary to take timing margins for these control signals into consideration, making it impossible to carry out a data outputting operation at high speed.
Moreover, when the activation timing of the output control signal is changed in accordance with the frequency of the clock signal, the data transfer timing of the circuitry on the preceding stage also needs to be adjusted. In order to carry out an accurate data transferring, it is necessary to take into consideration a margin for adjusted timing in the circuit on the preceding stage, making it impossible to implement a high speed operation.
The above-mentioned problem that the margin for a variation in delay time of detector enable signal DEN exerts an adverse effect on the high speed operability, becomes more conspicuous when the data outputting is performed in the double data rate mode. Specifically, when the data outputting is carried out in the double data rate mode, data of a plurality of bits, read in parallel with each other, needs to be converted to series data inside the output circuit, and the data needs to be latched in a parallel/serial conversion circuit at faster timing, and transferred to an output circuit. Since a high speed operability is required, the timing conditions with respect to the double data rate become more strict and it becomes impossible to ensure the high speed operability.
It is an object of the present invention to provide a synchronous type semiconductor memory device which can output data stably at high speed.
Another object of the present invention is to provide a synchronous type semiconductor memory device which can easily optimize the internal data reading timing.
Still another object of the present invention is to provide a synchronous type semiconductor memory device allowing data to be read accurately at high speed.
Further object of the present invention is to provide a semiconductor device which can transfer internal data accurately at high speed.
A semiconductor memory device in accordance with the first aspect of the present invention includes: a clock generation circuit for generating an output clock signal in accordance with a basic clock signal; a reading clock generation circuit for generating a reading clock signal from the basic clock signal in a manner different from the output clock signal; an internal reading circuit for transmitting data of a selected memory cell in a memory array in according with the reading clock signal to an internal data line; a latch circuit for latching data on the internal data line in accordance with the output clock signal; and an output circuit for transferring the latched data in the latch circuit in accordance with the output clock signal.
A semiconductor memory device in accordance with the second aspect of the present invention includes: a preamplifier circuit for amplifying data transferred from a memory array in response to a first clock signal generated in accordance with an external clock signal; and a shift circuit for transferring output data from the preamplifier circuit in response to a second clock signal. The second clock signal is a clock signal having a phase adjusted relative to the external clock signal.
A semiconductor memory device in accordance with the third aspect of the present invention includes: a first circuit for generating and outputting first data from applied data in accordance with a first clock signal generated from an external clock signal; and a second circuit for generating and outputting second data in accordance with the data generated by the first circuit, in accordance with a second clock signal that is generated from the external clock signal in a manner different from the first clock signal.
Applied data is latched or transferred by using a clock signal generated by adjusting in phase the basic clock signal or external clock signal. Thus, different from a construction utilizing a fixed delay adjusted in accordance with the frequency, even when the phase/frequency of the basic clock signal or the external clock signal is changed, the data taking-in timing of the internal data with respect to these clock edges can be fixed by taking the data transfer time into consideration so that it becomes possible to take in data accurately even when the frequency or phase of the basic clock signal is changed.
By setting the taking-in timing in a fixed manner, the signal transfer timing of the preceding circuit can be flexibly adjusted in response to the frequency of the clock signal, thereby making it possible to optimize the operation timing of the circuit on the preceding stage in accordance with the frequency of the clock signal.
Moreover, in the output circuit or the internal reading circuit, triggering signals are generated from the same clock signal so that the timing adjustment is easily carried out and the timing margin can be reduced. Thus, it becomes possible to ensure high speed operation.